Micro/amorphous/crystalline silicon heterojunction solar cells (Contributo in atti di convegno)

Type
Label
  • Micro/amorphous/crystalline silicon heterojunction solar cells (Contributo in atti di convegno) (literal)
Anno
  • 2002-01-01T00:00:00+01:00 (literal)
Alternative label
  • Rizzoli R, C. Summonte, E. Centurioni, D. Iencinella, A. Migliori, F. Zignani (2002)
    Micro/amorphous/crystalline silicon heterojunction solar cells
    in PV In Europe, Conference and Exhibition, Roma, 7-11 October 2002
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Rizzoli R, C. Summonte, E. Centurioni, D. Iencinella, A. Migliori, F. Zignani (literal)
Pagina inizio
  • 256 (literal)
Pagina fine
  • 259 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#titoloVolume
  • PV in Europe - From PV Technology to Energy Solutions (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • CNR-IMM-Bo - via Gobetti 101 - I-40129 Bologna, Italy Dip. Chimica Applicata e Scienza dei Materiali, University of Bologna, I-40136 Bologna, Italy (literal)
Titolo
  • Micro/amorphous/crystalline silicon heterojunction solar cells (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#isbn
  • 3-936338-12-4 (literal)
Abstract
  • A design of the heterojunction solar cell involving the use of a p+ ?c-Si emitter grown by VHF-PECVD at low temperature (170 °C) is studied, as an alternative to the well established a-Si:H / c-Si scheme. The results on the optimization of the micro / amorphous heterojunction device structure are reported. To achieve a good control of the p+ ?c-Si layer thickness and crystalline fraction and preserve a continuous a-Si:H layer, ~5 nm thick, the p layer deposition was carried out by a three step process (deposition + exposure to a H2 plasma + deposition), with varying the diborane percentage in the gas mixture during the deposition step, and the H2 exposure times. The heterojunction microstructure resulting from the optical simulation and from HRTEM and the corresponding solar cell characteristics are reported. On flat devices, including a totally amorphous i-layer and a p+ ?c-Si layer more than 50 nm thick, we obtained Voc up to 638 mV and efficiencies as high as 14%. Devices showing crystalline paths crossing the a-Si:H buffer layer and thinner p+ nanocrystalline layers (~20 nm thick) exhibit Voc up to 624 mV and efficiencies up to 13 %. (literal)
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