Physical mechanism of progressive breakdown in gate oxides (Articolo in rivista)

Type
Label
  • Physical mechanism of progressive breakdown in gate oxides (Articolo in rivista) (literal)
Anno
  • 2014-01-01T00:00:00+01:00 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi
  • 10.1063/1.4882116 (literal)
Alternative label
  • Palumbo, Felix; Lombardo, Salvatore; Eizenberg, Moshe (2014)
    Physical mechanism of progressive breakdown in gate oxides
    in Journal of applied physics
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Palumbo, Felix; Lombardo, Salvatore; Eizenberg, Moshe (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroVolume
  • 115 (literal)
Rivista
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#pagineTotali
  • 7 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroFascicolo
  • 22 (literal)
Note
  • ISI Web of Science (WOS) (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • Technion Israel Institute of Technology; Consiglio Nazionale delle Ricerche (CNR) (literal)
Titolo
  • Physical mechanism of progressive breakdown in gate oxides (literal)
Abstract
  • The definition of the basic physical mechanisms of the dielectric breakdown (BD) phenomenon is still an open area of research. In particular, in advanced complementary metal-oxide-semiconductor (CMOS) circuits, the BD of gate dielectrics occurs in the regime of relatively low voltage and very high electric field; this is of enormous technological importance, and thus widely investigated but still not well understood. Such BD is characterized by a gradual, progressive growth of the gate leakage through a localized BD spot. In this paper, we report for the first time experimental data and a model which provide understanding of the main physical mechanism responsible for the progressive BD growth. We demonstrate the ability to control the breakdown growth rate of a number of gate dielectrics and provide a physical model of the observed behavior, allowing to considerably improve the reliability margins of CMOS circuits by choosing a correct combination of voltage, thickness, and thermal conductivity of the gate dielectric. (C) 2014 AIP Publishing LLC. (literal)
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