Defect-Tolerant Array Structures for VLSI and WSI Architectures (Contributo in atti di convegno)

Type

• Prodotto della ricerca (Classe)
• Contributo in atti di convegno (Classe)

Label

• Defect-Tolerant Array Structures for VLSI and WSI Architectures (Contributo in atti di convegno) (literal)

Anno

• 1987-01-01T00:00:00+01:00 (literal)

Alternative label

• L. Ciminiera; C. Demartini; A. Valenzano (1987)
  Defect-Tolerant Array Structures for VLSI and WSI Architectures
  in 20th ACM-IEEE Hawaii International Conference on System Sciences (HICSS'87), Kailua-Kona, 6-9 Gennaio 1987
  (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori

• L. Ciminiera; C. Demartini; A. Valenzano (literal)

Pagina inizio

• 21 (literal)

Pagina fine

• 30 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#pagineTotali

• 10 (literal)

Note

• Scopu (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni

• L. Ciminiera, C. Demartini: Dip. di Automatica e Informatica, Politecnico di Torino, Torino, Italy A. Valenzano: Centro di Studi per l'Elaborazione Nuimerale dei Segnali, CENS-CNR, Torino, Italy (literal)

Titolo

• Defect-Tolerant Array Structures for VLSI and WSI Architectures (literal)

Abstract

• A redundant interconnection structure is introduced, which is suitable for being used to implement bi-dimensional arrays of processing elements, even in presence of faulty cells. It is intended for enhancing the yield of high density VLSI and WSI systems, by allowing to implement the bi-dimensional structures circumventing the defective parts. Theoretical bounds on the reconfiguration capabilities of the proposed structure are presented, and some practical consequences of them are illustrated. Then two different algorithms for structuring the circuit in presence of defective parts are introduced and their performance is evaluated by simulation results, in terms of probability of obtaining successful configurations. (literal)

Editore

• The Institute of Electrical and Electronics Engineers (IEEE) (Editore)

Prodotto di

• Institute of Electronics, Computer and Telecommunication Engineering (IEIIT) (Istituto)

Autore CNR

• ADRIANO VALENZANO (Persona)

Insieme di parole chiave

• Keywords of "Defect-Tolerant Array Structures for VLSI and WSI Architectures" (Insieme di parole chiave)

Incoming links:

Prodotto

• Institute of Electronics, Computer and Telecommunication Engineering (IEIIT) (Istituto)

Autore CNR di

• ADRIANO VALENZANO (Persona)

Editore di

• The Institute of Electrical and Electronics Engineers (IEEE) (Editore)

Insieme di parole chiave di

• Keywords of "Defect-Tolerant Array Structures for VLSI and WSI Architectures" (Insieme di parole chiave)