Standard JEDEC JESD61A.01 Isothermal Electromigration Test Procedure (Altro prodotto)

Type
Label
  • Standard JEDEC JESD61A.01 Isothermal Electromigration Test Procedure (Altro prodotto) (literal)
Anno
  • 2007-01-01T00:00:00+01:00 (literal)
Alternative label
  • Impronta M; Schafft H A (2007)
    Standard JEDEC JESD61A.01 Isothermal Electromigration Test Procedure
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Impronta M; Schafft H A (literal)
Pagina inizio
  • 1 (literal)
Pagina fine
  • 38 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#altreInformazioni
  • NOTE: a dummy ISBN code \"0000000000000\" has been introduced in order to force the PEOPLE software to accept this product as a valid product. In fact at the date of introduction the \"VQR\" menu of the PEOPLE software does not accept a product in case the ISSN or ISBN code are not present. Instead, the VQR procedure accepts a product as \"other\" (\"altro\" in Italian language), to be submitted to the assessment of peer review. The JESD61A 2007 standard represents a radical change with respect to the original JESD61. In collaboration with Harry Schafft, Maurizio Impronta has been involved in the preparation of the JESD61A 2007 for about two years, from 2005 to 2007. The attachment \"JESD61A 2007_documents.pdf\" was introduced since the standard does not directly credit Maurizio Impronta and Harry Schafft as authors. Only the bibliography shows \"M. Impronta\" as author of papers [3] and [4], exploiting the procedure proposed by the standard JESD61A 2007. Therefore, the attachment contains the documents automatically delivered to Maurizio Impronta during the ballot procedure and the final acknowledgment to Maurizio Impronta. Potential users of the standard: all the manufacturing companies in the field of semiconductors. (literal)
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  • 38 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • CNR-IMM, Sezione di Bologna; National Institute of Standards and Technology (NIST), USA. (literal)
Titolo
  • Standard JEDEC JESD61A.01 Isothermal Electromigration Test Procedure (literal)
Descrizione sintetica
  • The standard describes a measurement procedure for rapid electromigration tests exploiting the isothermal technique (ISOT) at wafer level. This method is particularly oriented to measurements on metallizations realized with Cu-damascene technology. Note: the authors submitted (\"sponsored\") this measurement standard to the JEDEC 14.2 Committee for the Wafer-Level Reliability. The standard has been approved by acclamation and published. (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#isbn
  • 0000000000000 (literal)
Abstract
  • The isothermal test is an accelerated electromigration test performed on microelectronic metallizations. In the isothermal test, an attempt is made to maintain a constant mean temperature of the line under test, by varying the stress current and hence the amount of Joule heating imparted to the line. Given a known and unvarying thermal resistance of the sample to the ambient, the isothermal test uses a feedback control to maintain a constant power dissipated in the metallization under test, so that a constant test line mean temperature is achieved. When the line resistance changes during the test, due to electromigration damage, the power is kept constant, by varying the stress current. This document presents an algorithm for conducting the isothermal test using computer-controlled instrumentation. The intent is to provide a complete description of a functional isothermal test algorithm that will allow a programmer to implement and start using an accelerated electromigration test with ease. The algorithm is derived from published and unpublished literature. Bibliographic references are listed in Annex C. This standard was formulated under the cognizance of JC-14.2 Committee on Wafer-Level Reliability and approved by the JEDEC Board of Directors (BoD) Ballot JCB-07-20. It was prepared with the contribution of the National Research Council of Italy, Institute for Microelectronics and Microsystems (CNR-IMM) of Bologna, Italy. The present revision JESD61A introduces significant technical changes from the previous edition (EIA/JESD61, April 1997) to make it applicable to copper as well as to aluminum metallizations. Substantive changes to the document are listed in Annex D. (literal)
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