http://www.cnr.it/ontology/cnr/individuo/prodotto/ID180730
Wide-band modelling of CMOS interconnections and voiding damages with the lumped element LE-FDTD method (Articolo in rivista)
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- Wide-band modelling of CMOS interconnections and voiding damages with the lumped element LE-FDTD method (Articolo in rivista) (literal)
- Anno
- 2004-01-01T00:00:00+01:00 (literal)
- Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi
- 10.1002/jnm.557 (literal)
- Alternative label
Alimenti F.; Impronta M.; Scorzoni A.; Roselli L. (2004)
Wide-band modelling of CMOS interconnections and voiding damages with the lumped element LE-FDTD method
in International journal of numerical modelling (Print); John Wiley & Sons, Ltd., Chichester (Regno Unito)
(literal)
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- Alimenti F.; Impronta M.; Scorzoni A.; Roselli L. (literal)
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- ISI Web of Science (WOS) (literal)
- Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
- 1- DIEI, University of Perugia, Italy.
2 - CNR IMM-LAMEL, Bologna, Italy. (literal)
- Titolo
- Wide-band modelling of CMOS interconnections and voiding damages with the lumped element LE-FDTD method (literal)
- Abstract
- This paper illustrates the application of a lumped element-finite difference time domain (LE-FDTD)
simulator to the wide-band modelling of CMOS interconnections. To achieve very accurate results the
short-open calibration (SOC) technique has been adopted. Specific parameters of a CMOS interconnection
laterally screened by a stack of metal vias have been extracted in the two cases of an unperturbed and a
purposely damaged metal line. The behaviour of void-like defects in the metal line has been also studied
using the fully three-dimensional capabilities of the simulator. It has been demonstrated that, at least in the
simulated cases, only the specific resistance is affected by damaging. (literal)
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