CODACS Project: A Demand-Data Driven Reconfigurable Architecture (Articolo in rivista)

Type
Label
  • CODACS Project: A Demand-Data Driven Reconfigurable Architecture (Articolo in rivista) (literal)
Anno
  • 2002-01-01T00:00:00+01:00 (literal)
Alternative label
  • Verdoscia Lorenzo (2002)
    CODACS Project: A Demand-Data Driven Reconfigurable Architecture
    in Lecture notes in computer science
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Verdoscia Lorenzo (literal)
Pagina inizio
  • 547 (literal)
Pagina fine
  • 550 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroVolume
  • 2400- (literal)
Rivista
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#note
  • Rapporto tecnico ISI-CNR n. 2002/25 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#descrizioneSinteticaDelProdotto
  • This paper presents CODACS (COnfigurable DAtaflow Computing System) architecture, a high performance reconfigurable computing system prototype with a highly scalable degree able to directly execute in hardware dataflow processes (dataflow graphs). The reconfigurable environment consists of a set of FPGA based platformprocessors created by a set of identical Multi Purpose Functional Units (MPFUs) and a reconfigurable interconnect to allow a straightforward one-to-one mapping between dataflow actors and MPFUs. Since CODACS does not support the conventional processor cycle, the platform-processor computation is completely asynchronous according to the dataflow graph execution paradigm proposed by the author. (literal)
Note
  • ISI Web of Science (WOS) (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • 1- ICAR-CNR (literal)
Titolo
  • CODACS Project: A Demand-Data Driven Reconfigurable Architecture (literal)
Abstract
  • This paper presents CODACS (COnfigurable DAtaflow Computing System) architecture, a high performance reconfigurable computing system prototype with a highly scalable degree able to directly execute in hardware dataflow processes (dataflow graphs). The reconfigurable environment consists of a set of FPGA based platformprocessors created by a set of identical Multi Purpose Functional Units (MPFUs) and a reconfigurable interconnect to allow a straightforward one-to-one mapping between dataflow actors and MPFUs. Since CODACS does not support the conventional processor cycle, the platform-processor computation is completely asynchronous according to the dataflow graph execution paradigm proposed by the author. (literal)
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