http://www.cnr.it/ontology/cnr/individuo/prodotto/ID86978
Stack Engineering of HfO2-based Charge Trapping Non-volatile Memory (Contributo in atti di convegno)
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- Stack Engineering of HfO2-based Charge Trapping Non-volatile Memory (Contributo in atti di convegno) (literal)
- Anno
- 2010-01-01T00:00:00+01:00 (literal)
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Russo U, Spiga S, Congedo G, Lamperti A, Salicio O, Fanciulli M (2010)
Stack Engineering of HfO2-based Charge Trapping Non-volatile Memory
in MRS Spring Meeting: Symposium G: Materials and Physics of Nonvolatile Memories, San Francisco, California, USA
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- Russo U, Spiga S, Congedo G, Lamperti A, Salicio O, Fanciulli M (literal)
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- Charge trapping (CT) memory is the most widely accepted evolution of the floating gate Flash memory concept toward the integration beyond the 32nm technology node [1]. In CT memories, the poly-Si floating gate is replaced by a trap rich dielectric, usually Si3N4. Although the most often adopted solution consists of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) stack, severe physical and technological constraints demand for improved device characteristics and strongly support the research for alternative material stacks. We investigate the adoption of HfO2 as the CT layer in a TaN/Al2O3/HfO2/SiO2/Si stack. Indeed hafnium oxide was already proposed as the CT layer due to its good CMOS process compatibility and promising electrical properties, which include electron traps availability and large dielectric constant[2]. However discordant results have been reported in the literature and the correlation between material and device properties is still unclear. In our work, the HfO2/Al2O3 stack is grown on 4.5nm thick SiO2/Si substrate by atomic layer deposition at 300°C. The HfO2 and Al2O3 films are deposited using an O3 based chemistry, while (MeCp)2Hf(Me)(OMe) and TMA are used, respectively, as Hf and Al sources. The stack physical properties are investigated as a function of film thickness and annealing temperature (Ta), which is needed for a good crystallization of the Al2O3 blocking layer. ToF-SIMS analyses revealed good thermal stability of the multilayer up to 950-1000°C, whereas diffusion phenomena take place at higher temperatures. The electrical properties of the memory stack are measured on large area capacitors, and correlated to the structural and chemical properties. Similarly to the physical properties, the device programming, erase and retention performances are characterized as a function of Ta and of the HfO2 layer thickness (tCT). An increase in Ta generally improves the programming efficiency for fast programming pulses, possibly due to a better performance of the fully crystallized Al2O3 blocking layer. However, high Ta values are also found to degrade retention, which can be related to material inter-diffusion in the stack and indicates that a careful choice of Ta is fundamental for device optimization. On the other hand, a variation of tCT in the 12-18 nm range, weakly affects programming performances, but can be effectively used to control the erase performances. Finally, the performance of HfO2 based CT memory devices are compared with standard TANOS stack of similar equivalent oxide thickness. The use of HfO2 films as the charge trapping layer instead of Si3N4 improves the gate sensitivity factor in the 15-18 V range, which is attractive for multilevel programming, and leads to longer retention, which supports the interest of HfO2-based CT memory for high-reliability applications. (literal)
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- Stack Engineering of HfO2-based Charge Trapping Non-volatile Memory (literal)
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