Effect of Thermal Annealing on the Electrically Active Profiles and Surface Roughness in Multiple Al Implanted 4H-SiC (Articolo in rivista)

Type
Label
  • Effect of Thermal Annealing on the Electrically Active Profiles and Surface Roughness in Multiple Al Implanted 4H-SiC (Articolo in rivista) (literal)
Anno
  • 2007-01-01T00:00:00+01:00 (literal)
Alternative label
  • Giannazzo F, Roccaforte F, Raineri V, Salinas D (2007)
    Effect of Thermal Annealing on the Electrically Active Profiles and Surface Roughness in Multiple Al Implanted 4H-SiC
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Giannazzo F, Roccaforte F, Raineri V, Salinas D (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • IMM-CNR Catania; STMicroelectronics Catania (literal)
Titolo
  • Effect of Thermal Annealing on the Electrically Active Profiles and Surface Roughness in Multiple Al Implanted 4H-SiC (literal)
Abstract
  • The evolution of the electrically active acceptor profiles and of the surface morphology in 4H-SiC implanted with multiple energy (from 550 to 40 keV) Al ions was investigated by the combined use of scanning capacitance microscopy (SCM) and atomic force microscopy (AFM), depending on the post-implantation annealing conditions at temperatures from 1400 C to 1650 C in Ar or Ar+SiH4 ambient. Medium Al concentrations (1E17-1E18 cm-3) were used to obtain uniformly doped p-well regions for n-channel MOSFETs applications, and the annealing conditions (temperature, furnace ramp rate annealing ambient) were optimised to achieve a surface roughness compatible with the device channel region. For the lowest annealing temperature, a peculiar shape of the acceptor profile was observed, with a lack of electrically active Al in the surface region and with two peaks corresponding to the projected ranges of the highest energy Al implants. The desired box like acceptor profile was achieved after the highest temperature annealing. The comparison between the morphological images show that the surface quality is preserved even after the highest temperature annealing process, thus confirming that the 1650 C annealing is the best process for the formation of a medium concentration p-well for power MOSFETs applications. (literal)
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