An Approach for the Specification, Verification and Synthesis of Secure Systems (Articolo in rivista)

Type
Label
  • An Approach for the Specification, Verification and Synthesis of Secure Systems (Articolo in rivista) (literal)
Anno
  • 2007-01-01T00:00:00+01:00 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi
  • 10.1016/j.entcs.2006.12.003 (literal)
Alternative label
  • [1] Martinelli F., [1] Matteucci I. (2007)
    An Approach for the Specification, Verification and Synthesis of Secure Systems
    in Electronic notes in theoretical computer science; Elsevier Science Publishers, Amsterdam (Paesi Bassi)
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • [1] Martinelli F., [1] Matteucci I. (literal)
Pagina inizio
  • 29 (literal)
Pagina fine
  • 43 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroVolume
  • 168 (literal)
Rivista
Note
  • Scopu (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • [1] IIT-CNR, Pisa, Italy (literal)
Titolo
  • An Approach for the Specification, Verification and Synthesis of Secure Systems (literal)
Abstract
  • In this paper we describe an approach based on open system analysis for the specification, verification and synthesis of secure systems. In particular, by using our framework, we are able to model a system with a possible intruder and verify whether the whole system is secure, i.e. whether the system satisfies a given temporal logic formula that describes its secure behavior. If necessary, we are also able to automatically synthesize a process that, by controlling the behavior of the possible intruder, enforces the desired secure behavior of the whole system. (literal)
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