On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique (Articolo in rivista)

Type
Label
  • On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique (Articolo in rivista) (literal)
Anno
  • 2009-01-01T00:00:00+01:00 (literal)
Alternative label
  • Giustolisi G., Falconi C., D'Amico A., Palumbo G. (2009)
    On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique
    in Analog integrated circuits and signal processing
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Giustolisi G., Falconi C., D'Amico A., Palumbo G. (literal)
Pagina inizio
  • 81 (literal)
Pagina fine
  • 90 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroVolume
  • 58 (literal)
Rivista
Note
  • ISI Web of Science (WOS) (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • Department of Electric, Electronic and System Engineering, University of Catania, Catania, Italy Department of Electronic Engineering, University of Tor Vergata, Rome, Italy (literal)
Titolo
  • On-chip low drop-out voltage regulator with NMOS power transistor and dynamic biasing technique (literal)
Abstract
  • We propose a NMOS low drop-out voltage regulator suitable for on-chip power management. The circuit does not requires any external components for achieving compensation since it is internally compensated. A dynamic biasing strategy and a clock booster allows to properly drive the NMOS power transistor in a power efficient fashion and without limiting the speed response of the regulator. Transistor level simulations confirm the effectiveness of the proposed approach (literal)
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