Study of nanocrystal memory integration in a Flash-like NOR device (Articolo in rivista)

Type
Label
  • Study of nanocrystal memory integration in a Flash-like NOR device (Articolo in rivista) (literal)
Anno
  • 2007-01-01T00:00:00+01:00 (literal)
Alternative label
  • Gerardi C, Lombardo S, Ammendola G, Costa G, Ancarani V, Mello D, Giuffrida S, Plantamura MC (2007)
    Study of nanocrystal memory integration in a Flash-like NOR device
    in Microelectronics and reliability
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Gerardi C, Lombardo S, Ammendola G, Costa G, Ancarani V, Mello D, Giuffrida S, Plantamura MC (literal)
Pagina inizio
  • 593 (literal)
Pagina fine
  • 597 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroVolume
  • 47 (literal)
Rivista
Note
  • ISI Web of Science (WOS) (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • ST Microelect, FTM R&D, I-95121 Catania, Italy; IMM-CNR, I-95121 Catania, Italy; ST Microelect, FTM Phys Lab, I-95121 Catania, Italy (literal)
Titolo
  • Study of nanocrystal memory integration in a Flash-like NOR device (literal)
Abstract
  • Si nanocrystal memory cells have been integrated in Flash-like stand-alone devices of 16 Mb along with high and low voltage CMOS logic circuitry. Process integration drawbacks such as nanocrystal residuals in the circuitry region have been eliminated by optimizing etching processes. The program/erase threshold voltage distributions of the memory sectors are well separated and narrow. The voltage distribution width is related to NC sizes, and bigger NCs induce cell reliability problems. Some reliability issues for endurance are also related to the use of ONO dielectric which acts as charge trapping layer, mainly causing program/erase window shift and threshold voltage distribution broadening during endurance. (literal)
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