Magnetic domain-wall racetrack memory for high density and fast data storage (Articolo in rivista)

Type

• Articolo in rivista (Classe)
• Prodotto della ricerca (Classe)

Label

• Magnetic domain-wall racetrack memory for high density and fast data storage (Articolo in rivista) (literal)

Anno

• 2012-01-01T00:00:00+01:00 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi

• 10.1109/ICSICT.2012.6466687 (literal)

Alternative label

• W.S. Zhao1, 2, Y. Zhang1,2, H-P Trinh1,2, J-O Klein1, 2, C. Chappert1, 2, R. Mantovan3, A. Lamperti3, R.P. Cowburn4, T. Trypiniotis4, M. Klaui5, J. Heinen5, B. Ocker6, D.Ravelosona1, 2 (2012)
  Magnetic domain-wall racetrack memory for high density and fast data storage
  in IEEE 11th International Conference on Solid-State and Integrated Circuit Technology
  (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori

• W.S. Zhao1, 2, Y. Zhang1,2, H-P Trinh1,2, J-O Klein1, 2, C. Chappert1, 2, R. Mantovan3, A. Lamperti3, R.P. Cowburn4, T. Trypiniotis4, M. Klaui5, J. Heinen5, B. Ocker6, D.Ravelosona1, 2 (literal)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#url

• http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466687 (literal)

Rivista

• IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (Rivista)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni

• 1. IEF, Univ Paris-Sud, Orsay, 91405, France 2. UMR 8622, CNRS, Orsay, 91405, France 3. Laboratorio MDM IMM CNR, I-20864 Agrate Brianza, MB, Italy 4. Univ Cambridge, Cavendish Lab, Cambridge CB3 0HE, England 5. Johannes Gutenberg Univ Mainz, Inst Phys, D-55099 Mainz, Germany 6. Singulus Technologies, 63796, Kahl am Main, Germany (literal)

Titolo

• Magnetic domain-wall racetrack memory for high density and fast data storage (literal)

Abstract

• The racetrack memory device is a new concept of Magnetic RAM (MRAM) based on controlling domain wall (DW) motion in ferromagnetic nanowires. It promises ultra-high storage density thanks to the possibility to store multiple narrow DWS per memory cell. By using read and write heads based on magnetic tunnel junctions (MTJ) with perpendicular magnetic anisotropy (PMA) fast data access speed can also be achieved. Thereby the racetrack memory can be used as universal storage to address both embedded and standalone applications. In this paper, we present the device physics, integration circuit and architecture designs of a racetrack memory based on MTJs with PMA. Mixed SPICE simulations at 65 nm node demonstrate the capabilities of this device to perform high performances. Finally, we compare the potential specifications of the racetrack memory with other advanced non-volatile memory technologies. (literal)

Prodotto di

• Institute for microelectronics and microsystems (IMM) (Istituto)

Autore CNR

• ROBERTO MANTOVAN (Unità di personale interno)
• ALESSIO LAMPERTI (Unità di personale interno)

Incoming links:

Prodotto

• Institute for microelectronics and microsystems (IMM) (Istituto)

Autore CNR di

• ROBERTO MANTOVAN (Unità di personale interno)
• ALESSIO LAMPERTI (Unità di personale interno)

Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#rivistaDi

• IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (Rivista)