Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors (Articolo in rivista)

Type
Label
  • Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors (Articolo in rivista) (literal)
Anno
  • 2006-01-01T00:00:00+01:00 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi
  • 10.1016/j.jnoncrysol.2005.10.050 (literal)
Alternative label
  • M. Cuscunà; G. Stracci; A. Bonfiglietti; A. di Gaspare; L. Maiolo; A. Pecora; L. Mariucci; G. Fortunato (2006)
    Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors
    in Journal of non-crystalline solids
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • M. Cuscunà; G. Stracci; A. Bonfiglietti; A. di Gaspare; L. Maiolo; A. Pecora; L. Mariucci; G. Fortunato (literal)
Pagina inizio
  • 1723 (literal)
Pagina fine
  • 1727 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroVolume
  • 352 (literal)
Rivista
Note
  • ISI Web of Science (WOS) (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • IFN-CNR (literal)
Titolo
  • Annealing temperature effects on the electrical characteristics of p-channel polysilicon thin film transistors (literal)
Abstract
  • In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200 degrees C, 250 degrees C, 350 degrees C and 450 degrees C) and annealing times. We found that optimal conditions were obtained at 350 degrees C, with transfer characteristics showing a subthreshold slope of 0.5 V/dec, field effect mobility > 100 cm(2)/Vs and threshold voltage around -3.5 V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350 degrees C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for V,(stress) - V-t = -4 V while bias-stress at V-g = V-t and vertical bar V-g(stress)vertical bar >> vertical bar V-ds(stress)vertical bar did not produce appreciable changes in both transfer and output characteristics. (literal)
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