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General architecture, implementation and performance of the digital feedback control in RFX (Articolo in rivista)
- Type
- Label
- General architecture, implementation and performance of the digital feedback control in RFX (Articolo in rivista) (literal)
- Anno
- 2000-01-01T00:00:00+01:00 (literal)
- Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi
- 10.1109/23.846144 (literal)
- Alternative label
Luchetta, A; Manduchi, G (2000)
General architecture, implementation and performance of the digital feedback control in RFX
in IEEE transactions on nuclear science; IEEE-INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS INC., 345 E 47TH ST, NEW YORK, NY 10017-2394 (Stati Uniti d'America)
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- Luchetta, A; Manduchi, G (literal)
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- E-ISSN: 1558-1578 (literal)
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- http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=846144 (literal)
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- ISI Web of Science (WOS) (literal)
- Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
- Consorzio RFX, Padua, Italy (literal)
- Titolo
- General architecture, implementation and performance of the digital feedback control in RFX (literal)
- Abstract
- RFX is a large toroidal machine in the European Programme for nuclear fusion research. It uses digital active feedback for both control of global magnetic configuration and correction of local magnetic field errors. These controls have different time requirements. Global controls must produce output reference waveforms with updating frequencies of some kSample/s and must allow a maximum delay between input and corresponding output of few ms. Conversely, the local controls need faster response with updating frequencies of the outputs up to 20 kSample/s and maximum delay of 200 mu s. The I/O requirements are also different, ranging from few to many tens of input signals, depending on the specific controls. A general scalable distributed architecture has been designed and realized for the RFX feedback control systems. It is based on processor networks implemented by means of Digital Signal Processors equipped with built-in facilities for interprocessor communication and connected to each other either directly or via a fiber-optic based network. The paper summarizes the design concepts of the system architecture and, after the description of the hardware and software structure, reports the performances obtained. (literal)
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