Compiling CHR to parallel hardware (Contributo in atti di convegno)

Type
Label
  • Compiling CHR to parallel hardware (Contributo in atti di convegno) (literal)
Anno
  • 2012-01-01T00:00:00+01:00 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi
  • 10.1145/2370776.2370798 (literal)
Alternative label
  • Triossi A., Orlando S., Raffaetà A., Fruhwirth T. (2012)
    Compiling CHR to parallel hardware
    in 14th Symposium on Principles and Practice of Declarative Programming, Leuven, Belgium, 19-21 September 2012
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Triossi A., Orlando S., Raffaetà A., Fruhwirth T. (literal)
Pagina inizio
  • 173 (literal)
Pagina fine
  • 184 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#url
  • http://dl.acm.org/ft_gateway.cfm?id=2370798&ftid=1290668&dwn=1&CFID=270343077&CFTOKEN=81034639 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#titoloVolume
  • PPDP'12 - Proceedings of the 2012 ACM SIGPLAN Principles and Practice of Declarative Programming (literal)
Note
  • Scopu (literal)
  • PuMa (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • DAIS, Università Ca' Foscari Venezia, Italy; DAIS, Università Ca' Foscari, Venezia, Italy; DAIS, Università Ca' Foscari Venezia, Italy; Institute Software Engineering and Compiler Construction, Ulm University, Germany; (literal)
Titolo
  • Compiling CHR to parallel hardware (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#isbn
  • 978-1-4503-1522-7 (literal)
Abstract
  • This paper investigates the compilation of a committed-choice rule- based language, Constraint Handling Rules (CHR), to specialized hardware circuits. The developed hardware is able to turn the intrin- sic concurrency of the language into parallelism. Rules are applied by a custom executor that handles constraints according to the best degree of parallelism the implemented CHR specification can of- fer. Our framework deploys the target digital circuits through the Field Programmable Gate Array (FPGA) technology, by first com- piling the CHR code fragment into a low level hardware description language. We also discuss the realization of a hybrid CHR inter- preter, consisting of a software component running on a general purpose processor, coupled with a hardware accelerator. The latter unburdens the processor by executing in parallel the most computa- tional intensive CHR rules directly compiled in hardware. Finally the performance of a prototype system is evaluated by time effi- ciency measures. (literal)
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