Characterization of Si-CeO2-YBCO Tri-layers Grown by Magnetron Sputtering (Articolo in rivista)

Type
Label
  • Characterization of Si-CeO2-YBCO Tri-layers Grown by Magnetron Sputtering (Articolo in rivista) (literal)
Anno
  • 2003-01-01T00:00:00+01:00 (literal)
Alternative label
  • Chiodoni A. , Andreone D. , Botta D. , Camerlingo C. , Fabbri F. , Gerbaldo R. , Ghigo G. , Gozzelino L. , Laviano F. , Minetti B. , Pirri C.F. , Tallarida G. , Tresso E. and Mezzetti E. (2003)
    Characterization of Si-CeO2-YBCO Tri-layers Grown by Magnetron Sputtering
    in IEEE transactions on applied superconductivity (Print)
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • Chiodoni A. , Andreone D. , Botta D. , Camerlingo C. , Fabbri F. , Gerbaldo R. , Ghigo G. , Gozzelino L. , Laviano F. , Minetti B. , Pirri C.F. , Tallarida G. , Tresso E. and Mezzetti E. (literal)
Pagina inizio
  • 2860 (literal)
Pagina fine
  • 2863 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroVolume
  • 13 (literal)
Rivista
Note
  • ISI Web of Science (WOS) (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • Politecn Torino, UdR Torino Politecn, INFM, INFN Sez Torino, I-10129 Turin, Italy Politecn Torino, Dipartimento Fis, I-10129 Turin, Italy Ist Elettrotecn Nazl, I-10135 Turin, Italy CNR, Ist Cibernet, I-80078 Pozzuoli, NA, Italy Enea Frascati, I-00044 Frascati, Roma, Italy INFM, Lab MDM, I-20041 Agrate Brianza, MI, Italy (literal)
Titolo
  • Characterization of Si-CeO2-YBCO Tri-layers Grown by Magnetron Sputtering (literal)
Abstract
  • Material aspects of heterostructural Si/CeO2 fabricated as buffered substrates for sputtered YBCO films, are studied by means of X-ray diffraction, AFM, Raman and SIMS-ToF analysis. Different Si/CeO2 layouts are chosen and tri-layers Si/CeO2/YBCO grown on the respective bi-layer substrates, are preliminary analyzed. Outstanding material issues suggest that in the framework of sputtering technology, epitaxy is out of reach for Si/CeO2/YBCO multi-layers. However, the results point towards the scalability/integrability of the technology with silicon processing when the main target consists of networking for integrated electronics. (literal)
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