Dual step EBL Gate fabrication technology for GaN-HEMT wideband applications (Articolo in rivista)

Type
Label
  • Dual step EBL Gate fabrication technology for GaN-HEMT wideband applications (Articolo in rivista) (literal)
Anno
  • 2011-01-01T00:00:00+01:00 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#doi
  • 10.1016/j.mee.2011.02.064 (literal)
Alternative label
  • D. Dominijanni (1), E. Giovine (1), A. Notargiacomo (1), A. Pantellini (2), P. Romanini (2), M. Peroni (2), A. Nanni (2) (2011)
    Dual step EBL Gate fabrication technology for GaN-HEMT wideband applications
    in Microelectronic engineering; ELSEVIER SCIENCE BV, PO BOX 211, 1000 AE AMSTERDAM, NETHERLANDS, AMSTERDAM (Paesi Bassi)
    (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#autori
  • D. Dominijanni (1), E. Giovine (1), A. Notargiacomo (1), A. Pantellini (2), P. Romanini (2), M. Peroni (2), A. Nanni (2) (literal)
Pagina inizio
  • 1927 (literal)
Pagina fine
  • 1930 (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroVolume
  • 88 (literal)
Rivista
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#numeroFascicolo
  • 8 (literal)
Note
  • ISI Web of Science (WOS) (literal)
Http://www.cnr.it/ontology/cnr/pubblicazioni.owl#affiliazioni
  • 1. CNR Istituto di Fotonica e Nanotecnologie, Rome 00156, Italy 2. SELEX Sistemi Integrati, Rome 00156, Italy (literal)
Titolo
  • Dual step EBL Gate fabrication technology for GaN-HEMT wideband applications (literal)
Abstract
  • The operation at frequencies above 100 GHz of electronic devices like transistors has been achieved both by using high electron mobility III-V semiconductor materials or heterostructures and by implementing fabrication techniques which strongly reduce parasitic capacitances between the device terminals, without increasing series resistances. The technology has been applied on different GaN high electron mobility transistor epiwafers, and the devices performances analyzed under their DC and RF characteristics, outlining that further semiconductor material optimization is mandatory to fully benefit the sub 1/4 micron Gate length for very high frequency operation advantage. (C) 2011 Elsevier B.V. (literal)
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